Todd Hahn CV

Todd T. Hahn

Texas Instruments Compiler Group, Software Design Engineer, 1999-present

Participated in the design of a 16-bit instruction set extension to the C6400 VLIW DSP architecture.

Responsible for rapidly prototyping the C/C++ compiler to evaluate impacts of ISA variations.
Responsible for designing and performing experiments to evaluate the performance and code size impact of ISA variations on compiled code.
Suggested various changes to the 16-bit instruction set extensions.
Responsible for the design, implementation, and testing of the C6400+ compression algorithm.

Responsible for the design, implementation, and testing of various code size optimizations to exploit the 16-bit instruction set extensions to the C6400 ISA. Achieved significant code size reductions.
Responsible for the creation and implementation of a root cause analysis process.
Continuously identifying areas for improvement in infrastructure, and process.
Jointly responsible for compiler implementation to utilize the C6400+ software pipeline loop buffer (SPLOOP).
Responsible for tuning code size and performance optimizations in the C6400+ compiler.
Continuously identifying potential optimizations and changes to existing optimizations.
Design, implementation, and testing of various back-end optimization algorithms.
Analysis and correction of numerous complex defects throughout the compiler tool chain (e.g. parser, codegen, assembler, linker).
Implemented a region-based liveness analysis and register allocation infrastructure.
Significant experience with:

Software pipelining and instruction scheduling on a VLIW processor
Various optimizations to improve the performance and code size of software pipelined loops
Splitting registers that are live-too-long in a software pipelined loop using alternatives to modulo-variable expansion
Representing a machine in a machine description language
Pattern-based tree matching (instruction selection) and in-house machine description languages
Generating directed, acyclic graphs (DAG/DDG) in preparation for instruction scheduling
Analyzing compiler behavior during back-end (code generation) phases and identifying areas for improvement
Dataflow analysis
Control-flow graph transformations
Program cache conflict miss reduction techniques and algorithms
Copy propagation (backward and forward)
Object-oriented design, STL, design patterns
Defensive software design
Code reviews, design reviews, functional reviews
Root cause analysis

Partitioning on a clustered architecture
Chaitin-Briggs-Torczon-Cooper-style register allocation; conflict graphs, preference graphs, register spilling
Agile/scrum paradigm

Teaching Assistant, University of Wisconsin–Madison Computer Sciences Department, 1997-1999

Lecturer, University of Wisconsin–Madison, Summer 1998

2008

Compilation Strategies for Reducing Code Size on a VLIW Processor with Variable Length Instructions, Todd T. Hahn, Eric Stotzer, Dineel Sule, Mike Asal: Published in The 3rd International Conference on High Performance Embedded Architectures and Compilers (HiPEAC 2008) in Gothenburg, Sweden

Patent 7,581,082: Software Source Translator Selects Instruction Word Sizes, Todd T. Hahn, Eric J. Stotzer, Michael D. Asal
Patent 7,673,119: VLIW optional fetch packet header extends instruction set space, Michael D. Asal, Eric J. Stotzer, Todd T. Hahn
Patent application 20070022413: Tiered Register Allocation, Dineel Diwakar Sule, Eric J. Stotzer, Todd T. Hahn

Texas Instruments Systems and Software Series, 2010
Texas Instruments Developers Conference, 2006
Texas Instruments DSP Champs Conference, 2005, 2006
Conference paper, 2008 International Conference on High Performance Embedded Architectures and Compilers (see Publications)

Masters of Science in Computer Sciences, University of Wisconsin–Madison
Bachelors of Science in Computer Science, Michigan Technological University, Summa Cum Laude